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16 units · 51 lessons

Digital Logic Design

Digital Logic Design from the first idea to exam level: every lesson builds on the one before, with a worked example, a step-through diagram where it helps, a quick check and practice that adapts to what you know. Follows Mano & Ciletti, Digital Design (with Floyd, Digital Fundamentals).

Digital Logic Design at a glance

What does Digital Logic Design cover?

Number Systems, Binary Arithmetic & Codes, Logic Gates, Boolean Algebra, Canonical Forms & K-Maps, Combinational Circuits, Decoders, Encoders & Multiplexers, Latches & Flip-Flops, Sequential Circuit Design, Registers & Counters, Memory & Programmable Logic and Timing & Verilog. It follows Mano & Ciletti, Digital Design (with Floyd, Digital Fundamentals).

How many lessons does the Digital Logic Design course on Studious have?

16 units and 51 lessons, from "Analog, digital and why binary" to "Clocking, setup and hold time". Each lesson has a worked example, a quick check and practice that adapts to what you know, and many have step-by-step diagrams.

Course outline

  1. Unit 1 · Week 1

    Digital Systems and Number Systems

    1. Analog, digital and why binary
    2. Binary, octal and hexadecimal
    3. Converting between number bases
  2. Unit 2 · Week 2

    Binary Arithmetic and Codes

    1. Binary addition, subtraction and multiplication
    2. Complements: 1's and 2's
    3. Signed numbers and overflow
    4. Binary codes: BCD, Gray, ASCII and parity
  3. Unit 3 · Week 3

    Logic Gates

    1. AND, OR and NOT
    2. NAND, NOR, XOR and XNOR
    3. Truth tables and timing diagrams
  4. Unit 4 · Week 4

    Boolean Algebra

    1. Postulates and basic theorems
    2. De Morgan's theorems and complements
    3. Simplifying expressions algebraically
  5. Unit 5 · Week 5

    Canonical and Standard Forms

    1. Minterms and maxterms
    2. Sum of products and product of sums
    3. NAND-only and NOR-only implementation
  6. Unit 6 · Week 6

    Karnaugh Maps

    1. Two- and three-variable K-maps
    2. Four-variable K-maps
    3. Don't-care conditions and POS simplification
    4. The Quine–McCluskey method
  7. Unit 7 · Week 7

    Combinational Logic Design

    1. The combinational design procedure
    2. Code converters
    3. Half and full adders
  8. Unit 8 · Week 8

    Arithmetic Circuits

    1. Ripple-carry adders and the adder-subtractor
    2. Carry look-ahead addition
    3. BCD adder and magnitude comparator
  9. Unit 9 · Week 9

    Decoders, Encoders and Multiplexers

    1. Decoders
    2. Encoders and priority encoders
    3. Multiplexers and demultiplexers
    4. Implementing functions with decoders and multiplexers
  10. Unit 10 · Week 10

    Latches and Flip-Flops

    1. Sequential circuits and the SR latch
    2. The D latch and edge-triggered D flip-flop
    3. JK and T flip-flops
  11. Unit 11 · Week 11

    Analysis of Sequential Circuits

    1. State equations, state tables and state diagrams
    2. Mealy and Moore machines
    3. Flip-flop excitation tables
  12. Unit 12 · Week 12

    Design of Sequential Circuits

    1. State reduction and assignment
    2. Designing with D flip-flops
    3. Designing with JK and T flip-flops
  13. Unit 13 · Week 13

    Registers

    1. Registers and parallel load
    2. Shift registers and serial transfer
    3. The universal shift register
  14. Unit 14 · Week 14

    Counters

    1. Ripple (asynchronous) counters
    2. Synchronous binary counters
    3. BCD, ring and Johnson counters
  15. Unit 15 · Week 15

    Memory and Programmable Logic

    1. RAM and ROM
    2. PLA and PAL
    3. Error detection and correction: Hamming code
  16. Unit 16 · Week 16

    Timing, Hazards and Verilog

    1. Propagation delay and hazards
    2. Introduction to Verilog
    3. Clocking, setup and hold time

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